1. Field of the Invention
The present invention relate to a semiconductor device manufacturing process, and particularly to removal of a salicide layer in a semiconductor device manufacturing process.
2. Description of the Prior Art
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Today's fabrication plants are producing devices having 0.35 μm, 90 nm, and even 65 nm feature sizes or smaller. As geometries shrink, semiconductor manufacturing methods often need to be improved.
As MOS devices have been integrated at a rapid speed, an existing process using polysilicon as a gate electrode has caused many problems such as high gate resistance, depletion of polysilicon, and boron penetration into a channel area. A known process including a metal gate electrode/high-k gate dielectric layer has been proposed to eliminate the poly depletion effect and to offer an option of a lower thermal budget process.
FIGS. 1 to 5 are cross-sectional views illustrating a MOS transistor 10 having a metal gate electrode fabricated according to a known process. Referring to FIG. 1, a polysilicon gate electrode 12 is formed on a semiconductor substrate comprising a silicon layer 16, and a shallow-junction source extension 17 and a shallow-junction drain extension 19 are formed in the silicon layer 16 at both sides of the polysilicon gate electrode 12 and separated by a channel region 22. Then, a spacer 32 is formed on both lateral walls of the polysilicon gate electrode 12, and source and drain regions 18 and 20 are formed in the silicon layer 16 at both sides of the polysilicon gate electrode 12 and border the shallow-junction source extension 17 and the shallow-junction drain extension 19. A gate dielectric layer 14 separates a gate electrode 12 from the channel region 22. A liner 30, generally comprising silicon dioxide, is interposed between the gate electrode 12 and the silicon nitride spacer 32. Subsequently, a metal silicide layer 42 is formed on the top of the polysilicon gate electrode 12 and the surface of the source and drain regions 18 and 20, and a silicon nitride cap layer 46 is formed on the entire area of the semiconductor substrate having the source and drain regions 18 and 20 and the shallow-junction source extension 17 and the shallow-unction drain extension 19, so that the polysilicon gate electrode 12 can be covered. Next, a dielectric layer 48 is formed on the nitride layer 46. The silicon nitride cap layer 46 is usually between about 300 and about 1000 Å (angstrom) in thickness, and is formed by a plasma enhanced chemical vapor deposition (PECVD) process.
Next, referring to FIG. 2, the metal silicide layer 42 and the dielectric layer 48 are polished by a CMP process until the top of the polysilicon gate electrode 12 is exposed. The CMP process is performed by over polishing so that the top of the polysilicon gate electrode 12 can be exposed completely.
Subsequently, referring to FIG. 3, the remaining polysilicon gate electrode 12 is removed by a plasma reactive ion etch (RIE) using chlorine or a wet polysilicon etch using conventional etch chemistry to form an opening (i.e. recess) 54. Referring to FIG. 4, a barrier metal layer 56 may be formed on the sidewall of the recess 54 and on the surface of the dielectric layer 48, the nitride layer 46, the spacers 32, and the liner 30, and then a metal layer 58 is deposited to fill the recess and on the barrier metal layer 56. Finally, referring to FIG. 5, the surplus portion of metal layer 58 is polished away, forming a MOS transistor 10 having a metal gate.
The fabrication method described above includes an integration flow of metal gate replacement process consisting of an ILD (inter-layer dielectric) CMP (chemical mechanical polishing) after a transistor being built, a removal of a metal silicide layer and a polysilicon plug, a metal layer deposition, and a metal CMP. However, it is very difficult to remove the metal silicide by a CMP process.
FUSI gates (fully silicided polysilicon gates) offer a potential metal gate alternative due to a relative simplicity of the integration process. Referring to FIG. 2, the metal silicide layer 42 on the top of the gate electrode 12 and the dielectric layer 48 are polished by a CMP process until the top of the polysilicon gate electrode 12 is exposed. Then, referring to FIG. 6, a metal layer 50 is deposited on the exposed region of the polysilicon gate electrode 12, the nitride layer 46, the spacers 32, the liner 30, and the dielectric layer 48. The metal layer 50 is usually less than about 1000 Å and, in some cases, may be between about 500 and about 1000 Å in thickness. The metal layer 50 may be a multilayer of Ti/TiN, Co/TiN, or Co/Ti/TiN.
A thermal treatment is performed on the substrate having the metal layer 50 to transform the polysilicon gate electrode into a metal silicide gate electrode 52. The thermal treatment process may be performed through two steps, i.e., a first step at a temperature of about 400° C. to about 600° C., and a second step using a rapid thermal process (RTP) at a temperature of about 800° C. to about 1000° C. Subsequently, the residual metal layer, which has not reacted, is removed. The resultant MOS transistor 15 having a fully silicided gate electrode is shown in FIG. 7.
In the fabrication method including a FUSI metal gate integration process described above, NiSi polycide is removed through a direct ILD CMP step and the full silicidaton of polysilicon is followed to form a NiSi metal gate. However, the difficulty to remove the metal silicide by a CMP process also exists in this method. It is very hard to control and polish the NiSi polycide layer with good removal uniformity directly using a CMP process.
Therefore, there is still a need for a better method to remove a salicide layer in a semiconductor device manufacturing process.